
#  https://openfpga.readthedocs.io/en/master/manual/file_formats/pcf_file/
ifeq ($(OS),Windows_NT)
export ICE_TOOLS_BIN=d:/msys64/mingw64/bin/
export ICESPROG = icesprog
else
export ICE_TOOLS_BIN=
export ICESPROG = icesprog 
endif 

TOOLCHAIN_PREFIX = D:/SysGCC/risc-v/bin/riscv64-unknown-elf-

rtl_src = ../rtl/top.v  
top = top

pcf_file = io.pcf

# EASY_SOFT 为空则软件编译App ， 如果非空，则 soft/$(EASY_SOFT).c 为要编译的软件
EASY_SOFT := 

START_TIME := $(shell cat /proc/uptime | awk -F "." '{print $$1}') # Makefile进入，获取时间戳

ICELINK_DIR = $(shell df | grep iCELink | awk '{print $$6}')
${warning iCELink path: $(ICELINK_DIR)}
ICELINK_DIR = H:/




all:clean synth prog_flash showruntime

gowin:clean firmware
	cd gowin20k && make 

help:
	@echo "---------------------------------------------------------------"
	@echo "make sim           使用verilog仿真"
	@echo "make               compile soft and synth and config FPGA"
	@echo "make firmware      compile soft (App)"
	@echo "make synth         synth FPGA"
	@echo "make prog_flash    icesprog prog fpga"
	@echo "make 8/12/36/72M   icesprog set sysclk freq"
	@echo "---------------------------------------------------------------"

firmware:
ifeq ($(EASY_SOFT),)
	@echo " ---------------------- Compile App ---------------------- "
	@mkdir -p build 
	@cd App && make && cp Debug/*.hex ../build/
else 
	@echo "Compile $(EASY_SOFT).c ................"
	@mkdir -p build
	$(TOOLCHAIN_PREFIX)gcc -Os -nostdlib -march=rv32i -mabi=ilp32 -o build/firmware.elf soft/firmware.S soft/$(EASY_SOFT).c --std=gnu99 -Wl,-Bstatic,-T,soft/firmware.lds,-Map,build/firmware.map,--strip-debug -lgcc
	$(TOOLCHAIN_PREFIX)objcopy -O binary build/firmware.elf build/firmware.bin
	$(TOOLCHAIN_PREFIX)size build/firmware.elf
	python3 soft/makehex.py build/firmware.bin 8192 > build/firmware.hex
endif

synth: firmware 
	mkdir -p build 
	cp *.pcf build 
	cd build && $(ICE_TOOLS_BIN)yosys -p "synth_ice40 -json synth.json -blif synth.blif "  $(rtl_src)
ifeq ($(OS),Windows_NT)
	cd build && $(ICE_TOOLS_BIN)nextpnr-ice40 --lp1k --package cm36 --json synth.json --pcf-allow-unconstrained --pcf $(pcf_file) --asc synth.asc --freq 36
else 
	cd build && arachne-pnr -d 1k -P cm36 -p $(pcf_file)  synth.blif -o synth.asc
endif
	cd build && $(ICE_TOOLS_BIN)icepack synth.asc synth.bin 


debug:
	./Serial.chai

prog_flash:
	$(ICESPROG) build/synth.bin

copy_flash:
	@echo "$(ICELINK_DIR)"
	@if [ -d '$(ICELINK_DIR)' ]; \
    then \
        cp build/synth.bin $(ICELINK_DIR); \
		echo "copy done" ;\
    else \
        echo "iCELink not found"; \
        exit 1; \
    fi

# 设置时钟频率
8M:
	$(ICESPROG) -c 1

12M:
	$(ICESPROG) -c 2

36M:
	$(ICESPROG) -c 3

72M:
	$(ICESPROG) -c 4


sim: firmware
	@mkdir -p build
	iverilog -o build/tb.vvp -y ./rtl/servbase -y ./rtl/serving -y ./rtl/ rtl/tb.v 
ifeq ($(EASY_SOFT),)
	cp App/Debug/firmware.hex build/firmware.hex 
endif 
	cd build && vvp tb.vvp 

showruntime:
	@current_time=`cat /proc/uptime | awk -F "." '{print $$1}'`; \
	time_interval=`expr $${current_time} - $(START_TIME)`; \
	runtime=`date -u -d @$${time_interval} +%Hh:%Mm:%Ss`; \
	echo "runtime: $${runtime} "

clean:
	@rm -rf build App/Debug
	@cd App && make clean 



